Images for Press Release

Agilent Technologies Introduces Industry's First Complete Analyzer, Exerciser Solution for PCI Express 2.0

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PCIe2 LTSSM Exerciser card

Image 1:
PCIe2 LTSSM Exerciser card
Shows the x1 to x16 LTTSM exerciser that can be used to generate training sequences at speed on all lanes:

  • Generating training sequences and ordered sets across any lane width
  • Effectively test link negotiation and dynamically change lane width

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PCIe2 Analyzer module

Image 2:
PCIe2 Analyzer module
This is the x1 to x16 analyzer module that is plugged into a 2 or 4 slot I/O module. The front panel shows the “smart activity indicator” per lane LEDs. The analyzer is used:

  • To reliably capture PCI Express traffic across any lane width @ 5 Gbit/s
  • For advanced triggering
  • To visualize context sensitive columns with easy flow views

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PCIe 2 Midbus 2.0

Image 3:
PCIe 2 Midbus 2.0
Agilent midbus 2.0 series of probes for PCIe2 designs using Soft Touch technology. This is used for probing the signal without changing or affecting the signal characteristics. It is a non-intrusive, passive, extremely low capacitive loading probe.

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Midbus 2.0 w. backplane

Image 4:
Midbus 2.0 w. backplane
This illustrates the use model of the Agilent midbus 2.0 probe being plugged into a passive backplane

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PCIe2 Protocol Analyzer

Image 5:
PCIe2 Protocol Analyzer
The x1 to x16 analyzer in the I/O module. The controller shows the standard analyzer GUI with the captured traffic

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PCIe LTSSM Exerciser in backplane

Image 6:
PCIe LTSSM Exerciser in backplane
The x1 to x16 exerciser. This shows the LTSSM exerciser use model utilizing a passive backplane and add-in card. The controller shows a link test being set-up on the left and the status flow diagram on the right

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The Agilent MXG vector signal generator provides the vector-modulated signals necessary to produce components for cellular communications or wireless connectivity systems. Optimized for manufacturing, the MXG vector offers the fastest switching speeds for increases in throughput; reliability and simplified self-maintenance to maximize uptime; and the best ACPR performance to allow more test margin and increases in yield.

Image 7:
Protocol & Logic Analyzer with P2L gateway
Unique Protocol and Logic functionality in a single solution. Meaningful data from the physical layer to the transaction domain:

  • Immediate feedback on the lane status by the per lane LED
  • Per-lane view showing 8b or K/D or 10b symbols. Will show data even before channel bonding is completed
  • Two “trigger-down-the-lane” patterns on selectable lane
  • Manual & Automatic Speed setting

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Related Information
  Press Release:

Agilent Technologies Introduces Industry's First Complete Analyzer, Exerciser Solution for PCI Express 2.0
(2006-September-26)
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